WAVE specification
WAVE v0.4 defines the instruction set, execution model, registers, memory ordering, binary encoding, and conformance requirements.
Instruction encoding
Section titled “Instruction encoding”Instructions contain one or two 32-bit words. The first word has this layout:
| Bits | Field |
|---|---|
| 31:24 | Opcode |
| 23:16 | Destination register |
| 15:8 | First source register |
| 7:4 | Modifier |
| 3 | Reserved |
| 2 | Predicate negation |
| 1:0 | Predicate register |
Register fields address r0 through r255. The second word holds additional operands, an immediate, or a memory scope, depending on the opcode. See Binary encoding.
Each wave has independent control flow state. Instructions act on active lanes and honor their predicates. Conversion mnemonics put the destination type first: cvt_f32_i32 converts an integer to a float.